1. Technical Field
The present invention relates to a latency control circuit of a semiconductor device.
2. Related Art
Various semiconductor devices (chips) do not operate alone, but operate while sending/receiving data (signals) to/from other peripheral semiconductor devices.
For example, when a memory controller gives a read command to a semiconductor memory device, the semiconductor memory device sends data stored therein to the memory controller. However, the semiconductor memory device cannot send the data to the memory controller as soon as it receives the read command. This is because the semiconductor memory device needs a time to internally call the stored data and prepare outputting of the stored data.
In order that a device A makes interaction with a device B, the device A requests the device B to perform an operation and the device B needs a predetermined standby time until it performs the operation in response to the request. The standby time is called a latency time. For example, when a memory controller gives a read command to a semiconductor memory device, the semiconductor memory devices performs an operation of outputting data after a time as long as column address strobe (CAS) latency CL from when the read command is input thereto.
That is, a read access time tAA is given as the product of CAS latency CL and a clock cycle.tAA=CL×tCK 
Latency is required for an interactive operation between the device A and the device B, and a circuit for controlling the latency is called a latency control circuit.
FIG. 1 illustrates a latency control circuit in accordance with the related art.
A command decoder 110 outputs a pulse type of a read signal PREAD by receiving and decoding a read command RD. The read signal PREAD is simultaneously provided to a memory bank 130 and a latency counter 120. A time taken from the read command RD being input to the command decoder 110 to the read signal PREAD being output from the command decoder 110 is called a command decoder delay time tCD.
The latency counter 120 includes a plurality of flip-flops connected in series, and receives the read signal PREAD and outputs a latency signal LATENCY. The number of the flip-flops depends on the CAS latency CL.
A delay locked loop 140 receives a clock signal CK and outputs a delay locked loop clock signal DLLCLK.
A serializer 160 outputs an output data signal DQ fitting to the latency signal LATENCY by sampling and converting data, which is read out from the memory bank 130, into high-speed serial data, in response to the delay locked loop clock signal DLLCLK. The serializer 160 is also called a clock tree, so that a delay time taken by the serializer 160 is called a serializer delay time tCT. The memory bank 130 includes a bit line sense amplifier BLSA, a local sense amplifier LSA, and an input/output (I/O) sense amplifier IOSA. A latency clock generator 150 generates multi-phase sampling clocks LATCK1, LATCK2, . . . , and LATCK(CL-LO) based on the delay locked loop clock signal DLLCLK.
FIG. 2 illustrates a timing diagram of the latency control circuit of FIG. 1. The latency counter 120 compensates for the command decoder delay time tCD and the serializer delay time tCT using the multi-phase sampling clocks LATCK[1:CL-LO].
The reason of compensating for the command decoder delay time tCD and the serializer delay time tCT is as follows. Changes in the command decoder delay time tCD and the serializer delay time tCT depend on changes in manufacturing process, voltage and temperature PVT. Therefore, it is necessary to compensate for the command decoder delay time tCD and the serializer delay time tCT in an internal circuit such that the changes are not exposed to the outside, in order to satisfy a formula relating to the read access time tAA. The interval between pulses in each of the multi-phase sampling clocks LATCK[1:CL-LO] is generally smaller than one clock cycle tCK of the clock signal CK, and the sum of differences between the intervals and the clock cycle tCK becomes the same as the sum of the command decoder delay time tCD and the serializer delay time tCT.
When a minimum data delay value from data input to data output of a flip-flop in the latency counter 120 is defined as a shifting delay of the flip-flop, the shifting delay is the same as the sum of a setup time tSETUP of the flip-flop and a clock-to-q delay tCLK2Q of the flip-flop. That is, the shifting delay is described as follows.Shifting delay=tSETUP+tCLK2Q 
Therefore, a time taken from the read signal PREAD being input to the latency counter 120 to the latency signal LATENCY being output from the latency counter 120 is the same as the sum of the shifting delays of the flip-flops in the latency counter 120.
As a result, the latency control circuit forms a path for outputting the output data signal DQ after receiving the read command RD, and a total delay time Dtotal of the latency control circuit, which is generated in the entire path, is described as follows.Dtotal=tCD+(sum of shifting delays of flip-flops)+tCT
Meanwhile, the total delay time Dtotal should be smaller than the read access time (tAA=CL×tCK). That is,Dtotal<(CL×tCK).
However, as a semiconductor device is stabilized after the specifications thereof are fixed, a data rate increases and a clock cycle tCK decreases. Therefore, it is difficult to satisfy the above formula when the CAS latency CL increases. That is, it is difficult to maintain the total delay time Dtotal to be smaller than CL×tCK. In particular, the lower a supply power, the larger values of the command decoder delay time tCD, the shifting delay of the flip-flop, and the serializer delay time tCT, so that it is more difficult to satisfy the above formula.